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ref: Harrison-2003.06 tags: CMOS amplifier headstage electrophysiology neural_recording low_power chopper Reid Harrison date: 01-16-2012 04:43 gmt revision:12 [11] [10] [9] [8] [7] [6] [head]

IEEE-1201998 (pdf) A low-power low-noise CMOS amplifier for neural recording applications

  • detail novel MOS-bipolar pseudoresistor element to permit amplification of low-frequency signals down to milihertz range.
  • 80 microwatt spike amplifier in 0.16mm^2 silicon with 1.5 um CMOS, 1 microwatt EEG amplifier
  • input-referred noise of 2.2uV RMS.
  • has a nice graph comparing the power vs. noise for a number of other published designs
  • i doubt the low-frequency amplification really matters for neural recording, though certainly it matters for EEG.
    • they give an equation for the noise efficiency factor (NEF), as well as much detailed background.
    • NEF better than any prev. reported. Theoretical limit is 2.9 for this topology; they measure 4.8
  • does not compare well to Medtronic amp: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=197005915
    • 2 microwatt! @ 1.8V
    • chopper-stabilized
    • not sure what they are going to use it for - the battery will be killed it it has to telemeter anything!
    • need to find the report for this.
  • tutorial on chopper-stabilized amplifiers -- they have nearly constant noise v.s. frequency, and very low input/output offset.
  • References: {1056} Single unit recording capabilities of a 100 microelectrode array. Nordhausen CT, Maynard EM, Normann RA.
  • [5] see {1041}
  • [9] {1042}
  • [12] {1043}

Harrison, R.R. and Charles, C. A low-power low-noise CMOS amplifier for neural recording applications Solid-State Circuits, IEEE Journal of 38 6 958 - 965 (2003)

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ref: Dagtekin-2001 tags: recording chopper asic date: 01-15-2012 05:32 gmt revision:3 [2] [1] [0] [head]

IEEE-1019051 (pdf) A multi channel chopper modulated neural recording system

  • Presented herein is a fully integrated low-noise CMOS multi-channel amplifier for neural recording applications. The circuit employs the chopper modulation technique to reduce the effect of flicker noise and DC offset. A reduced area design implementation is achieved by trading off the increased noise margin performance of the chopper modulator for minimal amplifier area and analog multiplexing of the recording sites. A fully differential topology is used for the signal path to improve noise immunity. The analog amplifier exhibits 56 dB of gain with a 115 kHz bandwidth and a common mode rejection ratio (CMRR) of 80 dB. Simulation results show a total input referred noise less than 16 nV/√Hz. The system power consumption is approximately 750 μWatts. The fully integrated system was designed in ABN 1.6-μm single poly n-well CMOS process.


Dagtekin, M. and Wentai Liu and Bashirullah, R. Engineering in Medicine and Biology Society, 2001. Proceedings of the 23rd Annual International Conference of the IEEE 1 757 - 760 vol.1 (2001)