IEEE-1052646 (pdf) An implantable multielectrode array with on-chip signal processing
- "The major reason for the slow progress in the understanding of neural circuits has been the lack of adequate instrumentation."
- previous photolithographic: [4],[5]. Their first publication: [7].
- Kensall Wise, not Stephen.
- Single shank
- 10 recording sites spaced at 100um
- Amplifying 100x, b/w 15kHz., multiplexing.
- width: 15um near tip, 160um at base.
- 3 leads (!) power, ground, data.
- 6um LOCOS enhancement and depletion NMOS technology -- not CMOS. (latter is prone to latch-up)
- 5mW power.
- boron dope silicon, etch back non doped portion with ethylenediamine-pyrocatechol (EDP) water solution.
- must not have any substrate bias!
____References____
Najafi, K. and Wise, K.D. An implantable multielectrode array with on-chip signal processing Solid-State Circuits, IEEE Journal of 21 6 1035 - 1044 (1986) |