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ref: Seymour-2007.09 tags: neural probe design recording Kipke Seymour parelene MEA histology PEDOT date: 02-23-2017 23:52 gmt revision:13 [12] [11] [10] [9] [8] [7] [head]

PMID-17517431[0] Neural probe design for reduced tissue encapsulation in CNS.

  • See conference proceedings too: PMID-17947102[1] Fabrication of polymer neural probes with sub-cellular features for reduced tissue encapsulation.
    • -- useful information.
  • They use SU8 - photoresist! - as a structural material. See also this.
    • They use silicon as a substrate for the fabrication, but ultimately remove it. Electrodes could be made of titanium, modulo low conductivity.
  • Did not / could not record from these devices. Only immunochemistry.
  • Polymer fibers smaller than 7um are basically invisible to the immune system. See [2]
  • Their peripheral recording site is 4 x 5um - but still not invisible to microglia. Perhaps this is because of residual insertion trauma, or movement trauma? They implanted the device flush with the cortical surface, so there should have been little cranial tethering.
  • Checked the animals 4 weeks after implantation.
  • Peripheral electrode site was better than shank location, but still not perfect. Well, any improvement is a good one...
  • No statistical difference between 4x5um lattice probes, 10x4um probes, 30x4um, and solid (100um) knife edge.
    • Think that this may be because of electrode micromotion -- the lateral edge sites are still relatively well connected to the thick, rigid shank.
  • Observed two classes of immune reactivity --
    • GFAP reactive hypertrophied astrocytes.
    • devoid of GFAP, neurofilament, and NEuN, but always OX-42 and often firbronectin and laminin positive as well.
    • Think that the second may be from meningeal cells pulled in with the stab wound.
  • Sensitivity is expected to increase with decreased surface area (but similar low impedance -- platinum black or oxidized iridium or PEDOT {1112} ).
  • Thoughts: it may be possible to put 'barbs' to relieve mechanical stress slightly after the probe location, preferably spikes that expand after implantation.
  • His thesis {1110}

____References____

[0] Seymour JP, Kipke DR, Neural probe design for reduced tissue encapsulation in CNS.Biomaterials 28:25, 3594-607 (2007 Sep)
[1] Seymour JP, Kipke DR, Fabrication of polymer neural probes with sub-cellular features for reduced tissue encapsulation.Conf Proc IEEE Eng Med Biol Soc 1no Issue 4606-9 (2006)
[2] Sanders JE, Stiles CE, Hayes CL, Tissue response to single-polymer fibers of varying diameters: evaluation of fibrous encapsulation and macrophage density.J Biomed Mater Res 52:1, 231-7 (2000 Oct)

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ref: -0 tags: asynchronous design Rajit Manohar Octasic date: 06-12-2013 00:19 gmt revision:5 [4] [3] [2] [1] [0] [head]

At Cornell I took a VLSI design class taught by Rajit Manohar (*), and even then - 2002/2003 - he was very excited about asynchronous circuit design. I was uncertain about the technology at the time, but generally I trusted his instinct. Seems that there is certainly some oil in those hills - Octasic has just released a new basestation IC based on asynchronous processor cores: http://www.octasic.com/en/products/oct2200/oct2224w.php

The associated product-brief/technology whitepaper gives some good motivations for why asynchronous design is superior to classical synchronous design: (I'll quote, since I find this fascinating, hope they don't mind!)

  • Elimination of clock trees - Synchronous high-speed processors require large clock trees to keep sequential blocks synchronized. These clock trees require high-power buffers to drive complex high-capacitance networks that cover most of the chip. Clocks change state twice per cycle, consuming power on both positive and negative edges. These clock trees do not perform any information processing, thus provide no useful computing work, yet they consume a significant portion of the total power. Eliminating the clock trees alone can reduce power consumption by as much as 40% in a high-performance processor.
  • Elimination of pipeline state elements - Modern synchronous high-performance processors rely heavily on pipeline design techniques. Those pipelines require the use of a very large number of inter-stage flip-flops and state elements to support a high clock frequency operation. However, these inter-stage flip-flops and state elements also dont contribute to the actual data processing and computing tasks performed by the processor. In an asynchronous design these storage elements are discarded, saving the silicon space they occupy and the large amount of power they consume.
  • Elimination of lost margin timing - These inter-stage flip-flops require set-up and hold times which force a significant portion of the time between clock edges to be unusable for computation in high-frequency synchronous designs. Moreover given that each sub-micron technology shrink tends to increase path timing uncertainty, this further shortens the active period that can be used to achieve useful work between clock edges. This also means that in a synchronous design, the inter-stage circuit logic needs to be designed to operate increasingly faster than a single clock period to perform the same work. This requires the increased use of larger, higher power buffers in the datapath. In an asynchronous processor design, the logic does not have to deal with such small time steps. They can be built using slower, smaller and lower power circuits, while still delivering the same level of overall performance. Because the gates can be slower, it allows more use of low-leakage high-threshold voltage (HVT) gates, which drastically reduces leakage and further reduces power consumption and die area.
  • Reducing wire interconnect length -The silicon area savings discussed above translate into even more power savings, because wires connecting two elements get shorter as the circuits between these elements shrink. Shorter wires have less capacitance, thus switching them requires less power by using smaller buffers

Cool! I expect to see these techniques in many processors in the future - from embedded, very power sensitive MCUs to GPUs!

(*) Rajit was a cool guy. Not only did he give us a good grade, but he even drove us 'downtown' (in the sense of down the hill, Ithaca doesn't really have a downtown) at one point to pick up some resistors and other electronic parts so we could test out MOSIS-fabricated ASIC.

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ref: -0 tags: active filter design Netherlands Gerrit Groenewold date: 02-17-2012 20:27 gmt revision:0 [head]

IEEE-04268406 (pdf) Noise and Group Delay in Actvie Filters

  • relevant conclusion: the output noise spectrum is exactly proportinoal to the group delay.
  • Poschenrieder established a relationship between group delay and energy stored in a passive filter.
  • Fettweis proved from this that the noise generation of an active filter which is based on a passive filter is appoximately proportional to the group delay. (!!!)

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ref: work-2009 tags: bipolar opamp design current control microstimulation date: 01-06-2012 20:13 gmt revision:15 [14] [13] [12] [11] [10] [9] [head]

Recently I've been working on a current-controlled microstimulator for the lab, and have not been at all satisfied with the performance - hence, I decided to redesign it.

Since it is a digitally current-controlled stimulator, and the current is set with a DAC (MCP4822), we need a voltage controlled current source. Here is one design:

  • Because the output of the DAC is ground-referenced, and there is no negative supply in the design, the input buffers must be PNP transistors. These level-shift the input (0-2V, corresponding to 0-400uA) + 0.65V ( V be ), and increase the current. Both are biased with 1uA here, though 10uA would also work (lazily, through 1M resistors - I've checked that these work well too). This sets the base current at about 10nA for Q2 and Q1.
  • Q3 and Q4 are a current-mirror pair. If Q1 Vb increases, Ie for Q3 will decrease, increasing Ib for Q4 and hence its Ic. This will decrease the base current in Q6 and Q5, as desired. On the other hand, increasing Q2 Vb will decrease Q4 Ic, increasing Ib in Q6 and Q5. The current mirror effects the needed negative feedback in the circuit. This mirror could also be implemented with PNP transistors, but it doesn't work as well as then the collector (which has voltage gain) is tied to the emitter of the input PNP transistors. Voltage gain is needed to drive Q5 / Q6.
  • Q5 & Q6 are Darlington cascaded NPN transistors for current gain. If Q6 is omitted, Ib in Q5 increases -> Ib in Q1 decreases -> Ic in Q3 decreases -> Ib in Q4 increases. This results in a set-point of Ib = 100nA in Q5 -> Ic ~10uA. (unacceptable for our task).

What I really need is a high-side regulated current source; after some fiddling, here is what I came up with:

  • V2 is from the DAC; for the testing, I just simulate with a votlage ramp. This circuit, due to the 5V biasing (I have 5V available for the DAC, hence might as well use it) works well up to about 4V input voltage - exactly what the DAC can produce.
  • Q1 and Q2 are biased through 1M resistors R6 and R8; their emitters are coupled to a common-emitter amplifier Q3 and Q4.
  • As the voltage across R1 increases, Ib in Q1 decreases. This puts more current through the base of Q4, increasing the emitter voltage on both Q3 and Q4. This reduces the current in Q3, hence reducing the current in Q5 -> the voltage across R1. feedback ;-)
  • I tried using a current mirror on the high-side, but according to spice, this actually works *worse*. Q5 & Q3 / Q4 have more than enough gain as it stands.
  • Yes, that's 100V - the electrodes we use have high impedance, so need a good bit of voltage to get the desired current.
  • Now, will need to build this circuit to verify that it actually works.

  • (click for the full image)
  • This simulates OK, but shows some bad transients related to switching - I'll have to inspect this more closely, and possibly tune the differential stage (e.g. remove the fast transient response - Q6 and Q12 seem to turn off before Q5 and Q11 do, which pulls the output to +50v briefly)

  • This is the biphasic, bipolar stimulator's response to a rising ramp command voltage, as measured by the current through R17. Note how clean the signal is :-) But, I'm sure that it won't look quite this nice in real life! Will try one half out on a breadboard to see how it looks.
  • Note I switched from NMOS switching transistors to NPN - Q15 and Q16 shunt the bias current from Q3/Q2 and Q8/Q9, keeping the output PNPs (Q5 and Q11). These transistors are in saturation, so they take 100-200ns to turn off, which should be fine for this application where pulse width is typically 100us.
  • I've fed the pull-down NPN base current from the positive supply here, so that as long as Q5 and Q11 are on, Q6 and Q12 are also on. The storage time here (not that it is much, the transistors are kept out of saturation via D1-4) helps to keep the mean difference in voltage between animal or stimulee's ground and isolated stimulator ground low. In previous stimulators the high-side was a near-saturation PNP, which pulled the voltage all the way to the positive supply when stimulation started. This meant that any stray capacitance had to be charged through the brain - bad!
    • Note this means that the emitter current through Q6 and Q12 is more than the current through R17 by that passed through Q14 and Q13. By design, this is 1/50th that through Q5 and Q11. This means that the actual stimulated current will be 95% of the commanded current, something which is easily corrected in software.

  • Larger view of the schematic. Still worried about stability - perhaps will need to add something to limit slew rate.
  • V2 on the right is the command voltage from the DAC.

  • The amplifier in figure 5 suffered from low bandwidth, primarily because the large resistors effected slow timeconstants, and because there was no short path to +50V from the high-side PNP transistors. This led to very slow turn-off times. To remedy this:
    • Bias current to Q3 & Q4 was increased (R6 & R8 decreased) -> more current to charge / discharge capacitance.
    • Common emitter resistor concomitantly decreased to 22k. This increases the collector current.
    • Pull-up resistors changed to a current mirror. This allows the current through Q4 to pull up the bases of Q5 and Q6, letting them turn off more quickly. If Q1 is off (e.g. voltage across R1 is high), Q4 will be on, and Q6 will source this current. etc.
  • With this done, I tested it on the breadboard & it oscillated. bad! Hence, I put a 1nf (10nf in the schematic) capacitor from the collector of Q3 to ground - hence limiting the slew rate. This abolished oscillations and led to a very pretty linear turn-on waveform.
  • However, the turn-off waveform was an ugly exponential. Why? With Q2 or Q10 fully on, Q3 will be off. Q4 will effectively recharge C1 through R7. As the voltage across R7 goes to zero, so does the charging current. Since I don't want to add in a negative supply, I simply shifted the base voltage of Q3 and Q4 using a diode, about as simple as you can get!
  • Eventually, I replaced R7 with a current source ... but this did not change the fall waveform that much; it is still (partially) exponential. Possibly this is from the emitter resistors on the high-side.

  • As of now, the final version - tested using surface mount devices; seems to work ok!
  • Note added transistor Q11 - this discharges / removes minority carriers from the base of Q8. Even though D1 and D2 guarantee a current-starved Q8 in previous designs, they leave no path to ground from the base, so this transistor was taking forever to turn off. This was especially the case when switching (recall this is one half of a H-bridge, and Q9 would actually be on the other side of the h-bridge), since the other sides' Q9 would push current, while Q8 would continue to conduct & sink current. This current through R1 would increase Q8 emitter voltage, reverse-biasing its' base-emitter junction, making the transistor take 100us of us to turn off. Bad, since the amplifier is intended to replicate 100us pulses! Anyway, Q11 neatly solves the problem (albeit with 100ns or so of saturated-switching storage time - something that Q10 has anyway).
  • D1 and D2 are no longer really necessary, but I've left them in this diagram for illustrative purposes. (and they improve storage time a bit).

  • Update as the result of testing. Changes:
    • Added emitter resistors on the two current mirrors (Q6, Q7; Q12, Q13). This eliminated stability problems
    • Changed the anti-saturation diodes to a resistor. This is needed as it takes some time for Q9 to turn off, and to avoid unbalanced currents through the electrode pairs, this charge should be pulled to ground through Q8. In the actual circuit, Q11 is driven with a 4-8us delayed version of the control signal V4 so that Q8 remains on longer than current source Q9.
    • Decreased C1 to 100pf; because the amplifier is more stable now, the slew rate can be increased.

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ref: notes-0 tags: NXT EMG design myopen date: 01-03-2012 02:49 gmt revision:33 [32] [31] [30] [29] [28] [27] [head]

devices:

devices that can be turned off & on to save power (e.g. actually disconnected from power through a P channel MOSFET. must be careful to tristate all outputs before disabling, otherwise we'll get current through the ESD protection diodes )

  1. ethernet
  2. usb reset
  3. usb host power
  4. RS 232
  5. LCD (or at least the 40ma, 6V LED -- the LCD can be disabled in software, and it only consumes 2-3 ma anyway.)
  6. core voltage boost 0.8v to 1.2V
  7. AFE

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ref: work-0 tags: emg_dsp design part selection stage6 date: 09-22-2010 20:09 gmt revision:9 [8] [7] [6] [5] [4] [3] [head]

"Stage 6" part selection:

  • B527 to replace the BF537 -- big difference are more pins + USB OTG high-speed port. The previous deign used Maxim's MAX3421E, which seems to drop packets / have limited bandwidth (or perhaps my USB profile is incorrect?)
    • available in both 0.8mm and 0.5mm BGA. which? both are available from Digi-key. Coarser one is fine, will be easier to route.
    • Does not support mobile SDRAM nor DDR SDRAM; just the vanilla variety.
  • Continue to use the BF532 on the wireless devices (emg, neuro)
  • LAN8710 to replace the LAN83C185. Both can use the MII interface; the LAN83 is not recommended for new designs, though it is in the easier-to-debug TQFP package. Blackfin EZ-KIT for BF527 uses the LAN8710.
    • comes in 0.5mm pitch QFN-32 package.
    • 3.3V and 1.2V supply - can supply 1.2V externally.
  • SDRAM: MT48LC16M16A2BG-7E:D, digikey 557-1220-1-ND 16M x16, or 4M x 16 bit X 4 banks.
    • VFBGA-54 package.
    • 3.3v supply.
  • converter: AD7689 8 channel, 16-bit SAR ADC. has a built-in sequencer, which is sweet. (as well as a temperature sensor??!)
    • Package: 20LFCSP.
    • Seems we can run it at 4.0V, as in stage4.
  • Inst amp: MCP4208, available MSOP-8 (they call it 8-muMax). can use the same circuitry as in stage2 - just check the bandwidth; want 2khz maybe?
  • M25P16 flash, same as on the dev board.
    • Digikey M25P16-VMN6P-ND : 150mil width SOIC-8
  • USB: use the on-board high-speed controller. No need for OTG functionality; FCI USB connector is fine. Digikey 609-1039-ND.

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ref: life-0 tags: art design bantjes vector color date: 07-23-2009 14:14 gmt revision:0 [head]

Marian Bantjes - kickass designer. Just see her business card! or Saks snowflake theme

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ref: bookmark-0 tags: blog resume inspire layout design date: 03-02-2009 16:42 gmt revision:1 [0] [head]

http://10ch.wordpress.com/2009/02/07/sometimes-i-go-big/

  • great examples of resumes, and the right attitude to go with them.
  • inforgraphic resume - cool!

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ref: engineering notes-0 tags: BGA PCB design blueCore bluetooth laser drilling CSR via clearance date: 03-19-2008 22:35 gmt revision:4 [3] [2] [1] [0] [head]

This is from the CSR reference design for the BlueCore5 chip.

They also note that you have to pay attention to the aspect ratio of the vias - with laser drilling, this means that they needed a 63um prepreg between layers 1 and 2 (ground), with start copper thickness of 18um.

PTH = plated-through-hole. (refers to a type of via)

For 0.8mm BGA, you can loosen the design rules to the following: "

Minimum track width0.125mm(*) local, 0.15mm global0.005"
Minimum clearance0.125mm(*)0.005"
Minimum thru-hole0.15mm hole, 0.4mm landing under BGA0.006" on 0.016"
0.25mm hole, 0.6mm landing global0.01" on 0.024"
Solder Mask opening0.075mm radius opening around pads0.003"
(*) note: For a 0.8mm BGA with 0.4mm diameter pads, this could technically be 0.133mm, but I prefer to round to 1/8mm or just about 0.005"

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ref: notes-0 tags: kicad C++ design hierarchy date: 01-18-2008 22:06 gmt revision:1 [0] [head]

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ref: bookmark-0 tags: DSP filter webdesign fisher book date: 12-12-2007 06:15 gmt revision:0 [head]

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ref: bookmark-0 tags: BGA PCB design via layout Intel power date: 07-14-2007 00:29 gmt revision:0 [head]

http://www.intel.com/technology/itj/2006/volume10issue02/art05_945GMS_SFF_Low_Voltage/p03_overview.htm

  • describes PCB layout for Intel mobile 945GMS chipset (the same that is in Ana's Macbook)
  • suggest 10/20/28 via (drill diameter/??/pad size, what units? think)
  • interesting information on the making of the die substrate, too (ultra-fine lines! 30um vias too?)
  • [http://www.intel.com/technology/itj/2006/volume10issue02/art05_945GMS_SFF_Low_Voltage/p07_gmch.htm shows a diagram of memory bandwidth usage - most of it is used to refresh the LCD, which costs power. This section also has useful & interesting information on minimizing power consumption.

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ref: notes-0 tags: low-power microprocessor design techniques ieee DSP date: 05-29-2007 03:30 gmt revision:2 [1] [0] [head]

http://hardm.ath.cx:88/pdf/lowpowermicrocontrollers.pdf

also see IBM's eLite DSP project.

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ref: notes-0 tags: kicad footprint generator pcb design date: 05-22-2007 02:51 gmt revision:1 [0] [head]

oh yea!!! nice work mate!!

http://www.rohrbacher.net/kicad/quicklib.php

btw, kicad is the shit - and it is now in Debian!! I love debian! I love kicad!

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ref: notes-0 tags: TMS coil design date: 04-27-2007 03:17 gmt revision:0 [head]

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ref: engineering-0 tags: schematic capture layout PCB design engineering date: 03-17-2007 23:44 gmt revision:0 [head]

http://archives.seul.org/geda/user/Aug-2005/msg00027.html

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ref: bookmark-0 tags: mirror reflective projection lens design NEC optics date: 0-0-2006 0:0 revision:0 [head]

http://www.nec.co.jp/techrep/en/journal/g06/n03/060319.html

very neat - and I'm surprised that they put all of this on the web! you can almost make one of these yourself with the information within.