experimential results with the Nordic nRF24l01 (recall, as per {477}, that all SPI signals have an in-line 100 ohm resistor on both the headstage and bridge)
- If the bridge is a transmitter & the headstage is a receiver, we let the DMA finish before asserting CE, we continuously pool the SPI bus on the headstage, and read the packet entirely in, then almost all packets get through (by my rough oscilloscope measuring). This requires 420us per packet, 290 to actually transmit the packet and 130 for SPI maneuvers.
- If this direction is reversed (normal: headstage is the transmitter & bridge is the receiver), the packet reliability is increased. The headstage takes 350us to transmit one packet -- 60us for SPI transation ( can run at a higher speed, as it the bus traces on that board are smaller). However, the reliability of the link in both regimes > 95%.
- If the fifo is filled (3 packets) on the headstage side, then CE is pulsed, only the first and third packet get through, with 320 us between each packet. again, SPI bus is polled on the bridge (receiver) side. Reception of the first packet is reliable, reception of the third is not so much. Clearing the RX fifo increases reliability of receiving the third packet.
- This is not affected by disabling 2-byte CRC.
- This is not affected by doing non-dma SPI transfers.
- If i press my finger on the crystal oscillator next to the nRF24l01 (presumably thereby affecting tuning, sometimes only the second packet is received , but still never all 3.
- Now, if we offer the same regime & listen for the IRQ pin to go low, then clear the status, the bridge receives all 3 packets, but not always - it only gets every other group of 3 packets.
- This is not affected by disabling CRC, nor does it seem to be affected by channel selection.
- This is dependent on clearing the RX fifo after reception -- of course, clearing the RX fifo while a packet is in the air will cause that packet to be rejected
- If the fifo is not filled (2 packets) on the headstage (= transmitter), then CE is pulsed, the first packet gets through, and the second one does, too (sometimes)
- This is not affected by disabling CRC nor by changing the radio channel.
- If the fifo is not filled (2 packets) on the bridge (= transmitter), then CE is pulsed, only the first packet gets through
- if we reverse the order - have the bridge send 3 packets over SPI then assert CE, and set the headstage to listen & immediately clear the IRQ on interception, the first packet is most always received, the third packet is usually received, but the second packet is never received.
- if we do the same as above, and read the entire packet over SPI & use polling to see when another packet is received, then once again both the first and second packets are received properly. The polling implies that noise from the SPI bus is not corrupting packet reception.
- Again, if we do pipelined transmission from headstage to bridge by keeping the fifo consistently full, then every other packet is dropped -- see {477}
I wish i had pictures for this.. wish i had a webcam!
finally, it is solved! how:
- don't clear the IRQ status multiple times
- don't poll the bus to see if there is a packet - wait for the IRQ pin, then read the packet in.
- don't clear the TX fifo or RX fifo, except in time of error or when starting up.
- keepin the fifo one-full works with a headstage (= transmitter) SPI clock of 8.25mhz. at this rate, can upload 2 packets before 1 is transmitted.
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